1. Field of the Invention
The present invention relates to a method of and an apparatus for designing a test facile semiconductor integrated circuit with scan paths, and more particularly to a method of designing a scan path construction of a test facile semiconductor integrated circuit with scan paths.
2. Description of the Related Art
A known technique for applying a scan path test to a semiconductor integrated circuit which is divided into logic blocks will be described below with reference to FIG. 1 of the accompanying drawings.
As shown in FIG. 1, a semiconductor integrated circuit is divided into logic blocks A, B, C, D. If five scan paths are to be employed, then the five scan paths are incorporated in each of the logic blocks, and the scan paths in the logic blocks are interconnected in a highest layer. According to this technique, the numbers of scan paths in the logic blocks are equal to each other, but the area of interconnections used is large because as many interconnections as the number of divided scan paths extend between adjacent ones of the logic blocks. Details of this scan path technique are disclosed in Japanese laid-open patent publication No. 01-302850.
According to the disclosure, after layout and interconnection processes in the logic blocks are finished, the scan paths are constructed such that one scan path passes once through each logic block without passing a plurality of times through each logic block. In this example, the scan paths are constructed such that each divided scan path passes once through each logic block. Since the same number of scan paths are constructed in all the logic blocks, the area of interconnections between adjacent ones of the logic blocks is large.
Based on layout information of flip-flops (FFs) in the scan paths, the order of the FFs in the scan paths is changed for optimum connection in order to connect adjacent FFs.
According to Japanese laid-open patent publication No. 01-080884, a circuit is divided for advantageous test pattern generation, and scan paths are constructed from the circuit division information.
Japanese laid-open patent publication No. 02-282836 discloses an invention relating to the control of shifting operation. Japanese laid-open patent publications Nos. 03-059475 and 04-172266 reveal inventions relating to the technique of a method of controlling shifting operation.
According to another known process of designing a large-scale semiconductor integrated circuit, the circuit is divided into a plurality of logic blocks, a highest layer representing connection information between the logic blocks and an internal structure of each logic block are designed separately from each other, and thereafter their design data are combined with each other. There is also known a scan path test for large-scale semiconductor integrated circuits designed for testability. According to the scan path test, in order to control and observe the states of FFs in the circuit directly from outside of the circuit, all the FFs in the circuit are connected in series with each other into a shift register for facilitating the generation of a test pattern.
A period of time required by the scan path test increases in proportion to the length of the shift register constructed in the scan path test. The scan path test time can be reduced by a process of constructing a scan path such that the scan path is divided into a plurality of scan paths thereby to shorten each of the scan paths. Since the time to test the longest one of the divided scan paths becomes the time to test the semiconductor integrated circuit, the scan path needs to be divided into as equal scan paths as possible.
It is an object of the present invention to provide a method of designing a scan path construction of a test facile semiconductor integrated circuit with scan paths to determine the construction of scan paths assigned to logic blocks so as to minimize the overall length of interconnections between the logic blocks, from the number of scan paths, layout information of each of the logic blocks, and the number of FFs to be subjected to a scan path test within each of the logic blocks.
To achieve the object described above, there is provided in accordance with the present invention a method of designing a test facile semiconductor integrated circuit with scan paths, comprising the steps of counting the number of flip-flops to be subjected to a scan path test in each of logic blocks, calculating an average number of flip-flops per scan path from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit, reading pin layout information and floor plan information of each of the logic blocks, assigning a scan path to the logical blocks from a selected logic block serving as a start point, repeating the step of assigning a scan path to the logical blocks, and determining a scan path assigning arrangement in which the overall length of interconnections between the logic blocks is shortest, from the result of the division of scan paths.
If a fraction is produced when the average number of flip-flops per scan path is calculated from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit, then the number of flip-flops which is counted as residual of the division is preferably assigned one by one to the number of scan paths.
If a scan path of an equal length cannot be constructed in one logic block in the step of assigning a scan path to the logic blocks from a selected logic block serving as a start point, then flip-flops in shortage are preferably supplied from the next logic block for thereby constructing a scan path.
The step of repeating the step of assigning a scan path to the logic blocks from selected logic block serving as a start point, a scan path for all combinations of logic blocks preferably comprises the step of repeating the step of assigning a scan path for only combined adjacent logic blocks.
The method may further comprise the step of constructing a single scan path so as not to extend over a plurality of logic blocks as much as possible to determine a shortest expected length of interconnections between the logic blocks, in order to achieve a scan path division arrangement to minimize an area of interconnections between the logic blocks from the result of the division of scan paths.
The step of calculating an average number of flip-flops per scan path from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit may be replaced with the step of, if it is necessary to equalize the numbers of flip-flops contained in divided scan paths in the logic blocks, coupling the logic blocks in a combination capable of equalize the numbers of flip-flops contained in the divided scan paths.
According to the present invention, there is also provided an apparatus for designing a scan path construction of a test facile semiconductor integrated circuit with scan paths, comprising means for counting the number of flip-flops to be subjected to a scan path in each of logic blocks, means for calculating an average number of flip-flops per scan path from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit, means for reading pin layout information and floor plan information of each of the logic blocks, means for assigning a scan path in a combination of logic blocks from a selected logic block serving as a start point and another logic block, means for repeating the assigning of a scan path for all combinations of logic blocks, and means for determining a scan path assignment arrangement in which the overall length of interconnections between the logic blocks is shortest, from the result of the assignment of scan paths.
According to the present invention, there is further provided a recording medium which stores a control program for a method of designing a scan path construction of a test facile semiconductor integrated circuit with scan paths to determine assigned scan paths to minimize an area occupied with interconnection wiring among logic blocks due to the scan paths assigned to logic blocks, wherein the control program comprising the steps of counting the number of flip-flops to be subjected to a scan path in each of logic blocks, calculating an average number of flip-flops per scan path from the number of scan paths and the overall number of flip-flops in the semiconductor integrated circuit, reading pin layout information and floor plan information of each of the logic blocks, assigning a scan path to the logic blocks from a selected logic block serving as a start point in each combination of logic blocks, repeating the step of assigning a scan path for all combinations of logic blocks, and determining a scan path assigning arrangement in which the overall length of interconnections between the logic blocks is shortest, from the result of the division of scan paths.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.